Title :
Parallel simulated annealing: accuracy vs. speed in placement
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
fDate :
6/1/1989 12:00:00 AM
Abstract :
The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.<>
Keywords :
VLSI; circuit layout CAD; parallel algorithms; VLSI placement; accuracy; combining algorithms; connection Machine implementation; error measurements; local-memory implementation; parallel simulated annealing; parallelism; periodic synchronization; shared-memory implementation; speed; synchronization; task allocation; Circuit simulation; Computational modeling; Computer simulation; Costs; Optimization methods; Routing; Simulated annealing; Solids; Temperature; Tin;
Journal_Title :
Design & Test of Computers, IEEE
