Scan-path architecture for pseudorandom testing

The author presents an architecture for implementing scan technology in a state-of-the-art workstation that uses a single resource to control scan and clock functions and perform pseudorandom testing of individual chips and boards. The testing approach, which is based on the use of a linear-feedback shift register, also features the ability to capture test results and compress them into a single signature for comparison with a known ´golden-circuit´ signature. The author describes an application for testing the Apollo DN10000 and presents a list of design rules for pseudorandom testing at the board level. He discusses communication with scan and clock resources, timing relationships for scan operations, problems encountered, and design-for-testability issues in some depth.<>