Title :
Planar, fully ion-implanted InP junction FETs with a nitride-registered gate metallization
Author :
Boos, John B. ; Kruppa, Walter ; Molnar, B.
Author_Institution :
US Naval Res. Lab., Washington, DC, USA
Abstract :
A planar, fully ion-implanted indium phosphide (InP) junction FET (JFET) fabrication process is described, which utilizes n/sup +/ source-drain implantation, Be and Be/P p/sup +/ gate implantation, AuZn/Ni/TiW/Au nitride-registered gate metallization, and proximity rapid thermal annealing. Devices fabricated with this approach exhibited a maximum transconductance of 140 mS/mm, which is believed to be the highest reported for InP JFETs.<>
Keywords :
III-V semiconductors; incoherent light annealing; indium compounds; ion implantation; junction gate field effect transistors; metallisation; 140 mS; AuZn-Ni-TiW-Au; InP; InP:Be, P; JFET; maximum transconductance; n/sup +/ source-drain implantation; nitride-registered gate metallization; p/sup +/ gate implantation; proximity rapid thermal annealing; Etching; Fabrication; Gallium arsenide; Gold; Implants; Indium phosphide; JFETs; Metallization; Ohmic contacts; Transconductance;
Journal_Title :
Electron Device Letters, IEEE
