• DocumentCode
    1179487
  • Title

    A pipeline design for the realization of the prime factor algorithm using the extended diagonal structure

  • Author

    Lun, Daniel Pak-Kong ; Siu, Wan-chi

  • Author_Institution
    Dept. of Electron. Eng., Hong Kong Polytech., Hung Hom, Hong Kong
  • Volume
    43
  • Issue
    10
  • fYear
    1994
  • fDate
    10/1/1994 12:00:00 AM
  • Firstpage
    1232
  • Lastpage
    1237
  • Abstract
    In this brief contribution, an efficient pipeline architecture is proposed for the realization of the Prime Factor Algorithm (PFA) for digital signal processing. By using the extended diagonal feature of the Chinese Remainder Theorem (CRT) mapping, we show that the input data sequence can be directly loaded into a multidimensional array for the PFA computation without any permutation. Short length modules are modified such that an in-place and in-order computation is allowed. The computed results can then be directly restored back to the memory array without the need for further reordering. More importantly, the CRT mapping can also be used to represent the output data, hence we can utilize the extended diagonal feature of the CRT mapping to directly send the computed results to the outside world. As compared to the previous approaches, the present approach requires no shifting or rotation during the data loading and retrieval processes. In the case of multidimensional PFA computation, it does not require the computation to be split up into a number of two-dimensional computations. Hence, the overhead required for data loading and retrieval in each two-dimensional stage can be saved
  • Keywords
    parallel algorithms; parallel architectures; signal processing; Chinese Remainder Theorem; data loading; digital signal processing; input data sequenc; multidimensional array; pipeline architecture; pipeline design; prime factor algorithm; retrieval; Algorithm design and analysis; Cathode ray tubes; Circuit testing; Digital systems; Hazards; Logic circuits; Logic design; Pipelines; Signal processing algorithms; Solid state circuits;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.324549
  • Filename
    324549