Title :
0.3-μm mixed analog/digital CMOS technology for low-voltage operation
Author :
Ishii, Tatsuya ; Miyamoto, Masafumi ; Nagai, Ryo ; Nishida, Takashi ; Seki, Koichi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fDate :
10/1/1994 12:00:00 AM
Abstract :
A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si3N4 capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; ion implantation; metal-insulator-semiconductor devices; mixed analogue-digital integrated circuits; 0.3 micron; MOSFET structure; Si:As-Si3N4; Si3N4 capacitor-insulator; arsenic ion implantation; current drivability; double-polysilicon capacitor; junction capacitance; laterally doped buried layer; low-voltage operation; mixed analog/digital CMOS technology; polysilicon plate; threshold voltage; voltage coefficient; CMOS technology; Capacitance; Capacitors; Delay; Fluctuations; Impurities; Insulation; Low voltage; MOSFET circuits; Threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
