DocumentCode
1179989
Title
Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers
Author
Mutlu, Onur ; Moscibroda, Thomas
Author_Institution
Carnegie Mellon Univ., Pittsburgh, PA
Volume
29
Issue
1
fYear
2009
Firstpage
22
Lastpage
32
Abstract
Uncontrolled interthread interference in main memory can destroy individual threads´ memory-level parallelism, effectively serializing the memory requests of a thread whose latencies would otherwise have largely overlapped, thereby reducing single-thread performance. The parallelism-aware batch scheduler preserves each thread´s memory-level parallelism, ensures fairness and starvation freedom, and supports system-level thread priorities.
Keywords
batch processing (computers); parallel processing; random-access storage; scheduling; fair shared memory controllers; interthread interference; memory-level parallelism; parallelism-aware batch scheduling; system-level thread; Control systems; Degradation; Delay; Interference; Multicore processing; Parallel processing; Processor scheduling; Random access memory; System performance; Yarn; DRAM; chip multiprocessors.; fairness; memory controllers; memory-level parallelism; multicore; quality of service;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2009.12
Filename
4796166
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