DocumentCode :
1180423
Title :
An improved successive-approximation register design for use in A/D converters
Author :
Russell, Howard T., Jr.
Volume :
25
Issue :
7
fYear :
1978
fDate :
7/1/1978 12:00:00 AM
Firstpage :
550
Lastpage :
554
Abstract :
An improved design for a successive-approximation register (SAR) for use in A/D converters is presented. Thne proposed design is suitable for 
implementation such that a definite savings in devices is obtained over previous designs using the separate sequencer and code register approach. This particular design scheme operates in a fully synchronous mode with the clock allowing a reduction in propagation delay to be realized.
implementation such that a definite savings in devices is obtained over previous designs using the separate sequencer and code register approach. This particular design scheme operates in a fully synchronous mode with the clock allowing a reduction in propagation delay to be realized.Keywords :
A/D converters; ADC; Algorithms and circuits associated with AID conversion; Analog-to-digital conversion (ADC); Bipolar integrated circuits, logic; Analog-digital conversion; Clocks; Digital TV; Employment; Engineering profession; Laboratories; Motion pictures; Registers; Telephony; Videoconference;
fLanguage :
English
Journal_Title :
Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-4094
Type :
jour
DOI :
10.1109/TCS.1978.1084494
Filename :
1084494
Link To Document :
