DocumentCode :
1180609
Title :
Ultrashort SONOS memories
Author :
Moon Kyung Kim ; Chae, S.D. ; Chae, H.S. ; Kim, Moon Kyung ; Jeong, Y.S. ; Lee, JoWon ; Silva, H. ; Tiwari, Sandip ; Chung Woo Kim
Author_Institution :
Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
Volume :
3
Issue :
4
fYear :
2004
Firstpage :
417
Lastpage :
424
Abstract :
We report the operational characteristics of ultrashort SONOS memories down to ∼30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (∼120 mV/decade), and ∼2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 105 cycles for the smallest devices. The smallest structures tested employ ∼75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to ∼30-nm effective gate length, show very good endurance characteristics.
Keywords :
CMOS memory circuits; current density; nanostructured materials; semiconductor device measurement; semiconductor device testing; semiconductor storage; silicon-on-insulator; CMOS device scaling; SOI; drain-induced barrier; emission process; energy parameter; gate insulator; memory storage; memory window; nonvolatile memory; oxide-nitride-oxide stack thickness; process-induced damage; retention time; scaling limits; silicon-on-insulator technology; silicon-oxide-nitride-oxide-silicon memory; subthreshold swing; thin tunneling oxide; trapping center density; ultrashort SONOS memories; Electron traps; Insulation; Nanocrystals; Nonvolatile memory; Reproducibility of results; SONOS devices; Silicon on insulator technology; Testing; Tunneling; Voltage; CMOS device scaling; nonvolatile memory; scaling limits; silicon–oxide–nitride–oxide–silicon (SONOS) memory; silicon-on-insulator (SOI) technology;
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2004.834161
Filename :
1366341
Link To Document :
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