Title :
Diagnosis of multiple hold-time and setup-time faults in scan chains
Author_Institution :
Inst. of Electr. Eng., Nat. Taiwan Univ., Taiwan
Abstract :
This paper presents a diagnosis technique to locate hold-time (HT) faults and setup-time (ST) faults in scan chains. This technique achieves deterministic diagnosis results by applying thermometer scan input (TSI) patterns, which have only one rising or one falling transition. With TSI patterns, the diagnosis patterns can be easily generated by existing single stuck-at fault test pattern generators with few modifications. In addition to the first fault, this technique diagnoses remaining faults by applying thermometer scan input with padding (TSIP) patterns. For the benchmark circuits (up to 6.6 K scan cells), experiments show that the diagnosis resolutions are no worse than 15, even in the presence of multiple faults in a scan chain.
Keywords :
automatic test pattern generation; fault diagnosis; logic design; logic testing; ATPG; benchmark circuits; diagnosis patterns; multiple hold-time diagnosis; scan chains; setup-time fault diagnosis; stuck-at fault test pattern generators; thermometer scan input; Automatic test pattern generation; Benchmark testing; Circuit faults; Delay effects; Fault diagnosis; Flip-flops; Hardware; Manufacturing; Routing; Test pattern generators; ATPG; Index Terms- Fault diagnosis; scan chain.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2005.182