“Split ADC” Background Linearization of VCO-Based ADCs

A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs. Simulation results in a 45 nm CMOS process targeting 10 b and 12 b resolutions show ENOB of 9.58 b and 11.5 b, with convergence times for background calibration adaptation of 380 ms and 5.7 s, respectively. The background LMS procedure is tolerant of different input signals and provides linearity calibration over the range covered by the input signal excursion. An input dither of 3% of the ADC reference enables absolute accuracy in scale factor calibration. Design tradeoffs related to the VCO V-to-f characteristic, lookup table size, and convergence properties of the LMS adaptation loop are discussed.