DocumentCode
1181155
Title
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot
Author
Marchal, Paul ; Bougard, Bruno ; Katti, Guruprasad ; Stucchi, Associate Michele ; Dehaene, Wim ; Papanikolaou, Antonis ; Verkest, Diederik ; Swinnen, Bart ; Beyne, Eric
Author_Institution
IMEC VZW, Leuven
Volume
97
Issue
1
fYear
2009
Firstpage
96
Lastpage
107
Abstract
It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moore´s law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.
Keywords
circuit CAD; integrated circuit design; semiconductor industry; 3D technology assessment; path-finding; semiconductor industry; system design; Costs; Crystallization; Electronics industry; Foundries; Integrated circuit interconnections; Integrated circuit technology; Logic testing; Moore´s Law; Silicon carbide; Space technology; Design automation; design centering; integrated circuit design; technology assessment;
fLanguage
English
Journal_Title
Proceedings of the IEEE
Publisher
ieee
ISSN
0018-9219
Type
jour
DOI
10.1109/JPROC.2008.2007471
Filename
4796274
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