A low power built in repair analyzer for word oriented memories with optimal repair rate

High density memories are more prone to faults caused due to process variations or manufacturing defects. Such faults reduce yield as well as reliability. The failures in such memories are expensive due to wastage of large die area. These faults can be repaired by redundant memory locations. This paper presents a Built In Repair Analyzer for memory arrays using redundancy. A Built In Self Test block detects faults occurred, the Syndrome Storing Detector block distinguishes temporary and permanent faults. The permanent faults are alone repaired thus utilizing spare resources efficiently. The Must-Repair-Analysis (MRA) technique is done on fly during test, it stores faulty addresses and final analysis is done to find a solution to eliminate the analyzed faults. The BIRA module executes an efficient Redundancy Analysis algorithm to generate possible repair solutions. Further, power consumption is reduced using a novel low power Linear Feedback Shift Register (LFSR) which is a combination of Bit Swapping LFSR (BS-LFSR) and Dual Speed LFSR (DS-LFSR). The modified Dual Speed LFSR (MDS-LFSR) consists of two BS-LFSR´s, one is the slow speed BS-LFSR and another is the normal speed BS-LFSR each has independent clock rates. The modified DS LFSR lowers the transition density at the input side. Thus it reduces overall switching activity in Memory Under Test as well as reduces frequency of transitions of input patterns finally reducing the overall test power.