DocumentCode
1181904
Title
Wafer-applied underfill: flip-chip assembly and reliability
Author
Johnson, R. Wayne ; Qing Wang ; Ding, Fei ; Hou, Zhenwei ; Crane, Larry ; Tang, Hao ; Shi, Gary ; Zhao, Renzhe ; Danvir, Jan ; Qi, Jing
Author_Institution
Lab. for Electron., Auburn Univ., AL, USA
Volume
27
Issue
2
fYear
2004
fDate
4/1/2004 12:00:00 AM
Firstpage
101
Lastpage
108
Abstract
Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125°C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.
Keywords
failure analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; microassembling; surface mount technology; -55 to 125 C; Weibull plots; assembly process; capillary underfill; capital equipment; coating process; consumer electronic products; cure step; cycle time; failure analysis; flip-chip assembly; flip-chip reliability; floor space; liquid-to-liquid thermal cycle shock tests; organic substrate; surface-mount technology factory; thermal expansion coefficient mismatch; underfill dispense; wafer bumping; wafer sawing; wafer-applied underfill; Assembly; Consumer electronics; Electronic packaging thermal management; Manufacturing; Production facilities; Sawing; Space technology; Surface-mount technology; Testing; Thermal expansion; 65; Flip-chip; preapplied; underfill; wafer-applied;
fLanguage
English
Journal_Title
Electronics Packaging Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
1521-334X
Type
jour
DOI
10.1109/TEPM.2004.839599
Filename
1366493
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