Title :
Electrical stressing of submicrometre MOSFETs with raised source/drain structures realised by selective epitaxial growth of silicon using silane only
Author :
Waite, Andrew ; Evans, A.G.R.
Author_Institution :
Miocroelectronics Group, Southampton
fDate :
8/18/1994 12:00:00 AM
Abstract :
Submicrometre CMOS devices with raised source and drain (RSD) structures, realised by selective epitaxial growth (SEG) of silicon in silane have been electrically stressed. These devices were less susceptible to hot carrier degradation than their conventional counterparts, due to graded source and drain junctions
Keywords :
elemental semiconductors; insulated gate field effect transistors; semiconductor growth; silicon; vapour phase epitaxial growth; CMOS devices; Si; electrical stressing; graded source/drain junctions; hot carrier degradation; raised source/drain structures; selective epitaxial growth; silane; submicrometre MOSFETs;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940932
