• DocumentCode
    1181960
  • Title

    A scheduling heuristic for maximizing wirebonder throughput

  • Author

    Tovia, Fernando ; Mason, Scott J. ; Ramasami, Bashyam

  • Author_Institution
    Dept. of Ind. Eng., Univ. of Arkansas, Fayetteville, AR, USA
  • Volume
    27
  • Issue
    2
  • fYear
    2004
  • fDate
    4/1/2004 12:00:00 AM
  • Firstpage
    145
  • Lastpage
    150
  • Abstract
    Process planning and scheduling is an important part of managing the complex dynamic back end (i.e., test, assembly, and packaging) of the semiconductor manufacturing process. One of the most critical toolsets in the back end in terms of manufacturing capacity and product flow is the wirebonders that electrically connect bare silicon die to lead frames via thin metal wires. We develop two approaches for maximizing throughput on a group of wirebonders containing three different wirebonder types. Although our mathematical programming approach is capable of producing a near-optimal wirebonder schedule for any production day of interest, the computational requirements of this approach are unacceptable for implementation in a real-world back-end facility. Therefore, we develop a rule-based heuristic approach for wirebonder scheduling capable of producing high-quality schedules in a much shorter period of time.
  • Keywords
    deterministic algorithms; integrated circuit bonding; integrated circuit manufacture; lead bonding; mathematical programming; scheduling; semiconductor device manufacture; deterministic algorithms; lead frames; manufacturing capacity; manufacturing scheduling; mathematical programming; near-optimal wirebonder schedule; optimization methods; process planning; process scheduling; product flow; rule-based heuristic approach; scheduling heuristic; semiconductor manufacturing process; thin metal wires; wirebonder scheduling; wirebonder throughput maximization; Assembly; Dynamic scheduling; Job shop scheduling; Manufacturing processes; Process planning; Processor scheduling; Semiconductor device manufacture; Semiconductor device packaging; Semiconductor device testing; Throughput; 65; Deterministic algorithms; manufacturing scheduling; optimization methods;
  • fLanguage
    English
  • Journal_Title
    Electronics Packaging Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-334X
  • Type

    jour

  • DOI
    10.1109/TEPM.2004.837961
  • Filename
    1366498