Title :
Logarithmic speed modular multiplication
Author :
Walter, Colin D.
Author_Institution :
Comput. Dept., Univ. of Manchester Inst. of Sci. & Technol.
fDate :
8/18/1994 12:00:00 AM
Abstract :
A design for logarithmic speed modular multiplication is given and a quantitative comparison made with the best implementations of existing, more standard algorithms. A 40-fold increase in speed is reported using a chip area at the limit of current technology
Keywords :
digital arithmetic; multiplying circuits; algorithms; chip area; design; logarithmic speed modular multiplication;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940969
