Implementation of true single-phase clock D flipflops

A D flipflop is a basic element in logic design. The author presents a D flipflop implementation. Unlike a traditional implementation in which two complementary D latches are connected in series, the presented circuit is based on a single stage of precharged cascade differential voltage switch logic (CVSL). The main advantages of the D flipflop are that it has a true single phase clocking scheme, i.e. no clock inversion signal is needed, has a low clock load capacitance, and is glitch free and race free