• DocumentCode
    1182623
  • Title

    CMOS ternary dynamic NORA logic

  • Author

    Herrfeld, A. ; Hentschke, S.

  • Author_Institution
    Kassel Univ.
  • Volume
    30
  • Issue
    17
  • fYear
    1994
  • fDate
    8/18/1994 12:00:00 AM
  • Firstpage
    1370
  • Lastpage
    1371
  • Abstract
    A new ternary dynamic NORA-technique TDN has been developed which needs neither a complex clocking scheme nor buffering between successive stages. The complete TDN circuits for a one-trit multiplier and a sum mod-3 operator are presented
  • Keywords
    CMOS integrated circuits; integrated logic circuits; multiplying circuits; summing circuits; ternary logic; CMOS ternary dynamic NORA logic; TDN circuits; one-trit multiplier; sum mod-3 operator;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19940965
  • Filename
    326336
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1182623