Integrated hardware and software for improved flatness measurement with ATC4.1 flip-chip assembly case study

Over the past four decades, microelectronic packaging technology has evolved from peripheral, through-hole, and bulk configurations to area-array, surface-mount, and small-profile ones. Among these approaches, flip-chip attachment has become the most favorable choice for its large input/output capabilities and short signal path distributions. Given the prediction that the chip size and power of a single chip package will increase dramatically, substrate warpage of flip-chip packages during assembly and usage has become a major concern. Warpage could cause misalignment between the chip and the substrate, prevent the solder balls from making contact with the substrate flip-chip pads during the reflow soldering process, and induce crack nucleation at the board underfill interface during long-term usage. In this paper, the authors developed an integrated large-area shadow moire system for measuring small and large board and chip package warpage. The hardware is designed to carry out warpage measurement with a resolution on the order of micrometers. Combined with software, the integrated system is fully automated and highly accurate. For the case study, the system is used to characterize the substrate warpage of flip-chip on organic board assemblies. Warpage of substrates at the initial bare-board stage, post-reflow, and post-underfill is measured at room temperatures. It is found that by properly selecting initially warped substrates, post-reflow and post-underfill warpage can be reduced. In addition, warpage measurements at elevated temperatures during thermal cycling and power cycling show that power cycling poses a smaller impact on substrate warpage.