Realistic testability estimates for CMOS ICs

The authors highlight the importance of properly considering the probability of occurrence of faults in order to obtain an accurate estimate of the actual testability of a designed digital integrated circuit, along with adopting realistic parametric bridging fault modelling. The testability estimates performed on several benchmark circuits have shown that the equiprobable assumption for the fault occurrence leads to unnecessarily pessimistic values of expected fault coverage; hence, BIST design should be layout-driven, in order to obtain higher effectiveness of self-testing (improved defect coverage, and shorter test length)