Study of metal mask assisted TSV bottom the dielectric layer etching process

TSV CIS package technology is based on a via-last approach in association with an adapted bonding for optical applications. With the gradual increase of the CIS pixel and package integration density, CIS packaging requirements are also increasing. High aspect ratio TSV advantage is gradually reflected. The 3D stacking technology with TSV will be the future development trend of CIS package. In order to complete the bottom of the TSV etch process, we need to protect the wafer surface dielectric layer. In this paper, we use aluminum as a mask to protect the wafer surface silicon oxide dielectric layer. Aluminum with the thickness of 150nm doesn´t meet the requirement of the silicon oxide of TSV bottom etching. However, Aluminum with the thickness of 200nm and 300nm can play a role of the etching mask. And Aluminum mask with the thickness of 300nm can withstand 400s of etching time.