DocumentCode
1184355
Title
A variance minimization approach to tolerance design
Author
Iyer, Ravishankar Krishnan ; Downs, Thomas
Volume
27
Issue
9
fYear
1980
fDate
9/1/1980 12:00:00 AM
Firstpage
737
Lastpage
747
Abstract
This paper describes the development of a variance minimization strategy for the tolerancing of linear circuits and systems. The technique is conceptually simple and can be implemented through commonly available optimization routines. The applicability of the approach is illustrated through standard numerical examples. In addition the paper also derives a new expression for the variance of a system performance index.
Keywords
Computer-aided circuit analysis and design; Network tolerance assignment; Costs; Design engineering; Engineering drawings; Manufacturing processes; Process design; Quality control; Random variables; Statistical analysis; System performance; Systems engineering and theory;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/TCS.1980.1084887
Filename
1084887
Link To Document