A design of programmable logic arrays with universal tests

In this paper the problem of fault detection in easily testable programmable logic arrays (PLA\´s) is discussed. The easily testable PLA\´s will be designed by adding extra logic. These augmented PLA\´s have the following features: 1) for a PLA with inputs and columns (product terms), there exists a "universal" test set such that the test patterns and responses do not depend on the function of the PLA, but depend only on the size of the PLA (the values and ); 2) the number of tests is of order . For the augmented PLA\´s, universal test sets to detect faults in PLA\´s are presented. The types of faults considered here are single and multiple stuck faults and crosspoint faults in PLA\´s. Fault location and repair of PLA\´s are also considered.