Influence of compliant layer thickness on stress and strain of solder joints in wafer level chip scale package under thermal cycle

The 3D finite element analysis models of lead-free solder joint with compliant layer in wafer level chip scale package (WLCSP) were developed. Based on the models the lead-free solder joint with compliant layer stress and plastic strain were analyzed under thermal cycle. The results showed that: under thermal cycle loading conditions, the equivalent stress and equivalent plastic strain of the lead-free solder joint with compliant layer in wafer level chip scale package (WLCSP) distribution is uneven, the solder joints array maximum stress and strain area appears on the most distant from the center of the array of solder joints, the maximum stress and strain located in the far end at the bottom of the flexible lead-free solder joint contact with the PCB side of the edge. under thermal cycling loading conditions solder joints fatigue crack will give priority and extended in this area. In other structural parameters remain unchanged, lead-free solder joints thermal cycle maximum stress and strain decreases with the increase of 1st and 2nd compliant layer thickness.