Title :
Area-time efficient diminished-1 multiplier for Fermat number transform
Author :
Ashur, Ahmed S. ; Ibrahim, M.K. ; Aggoun, A.
Author_Institution :
Dept. of Electr. & Electron. Eng., Nottingham Univ.
fDate :
9/29/1994 12:00:00 AM
Abstract :
A new regular implementation of a diminished-1 multiplier is presented which requires less silicon area and achieves higher speed than existing designs. For a multiplier where the modulus involved is F 4, a 34% increase in the speed of operation is achieved in comparison to that of Sunder et al (see IEE Proc. G, vol. 140, no. 3, p. 211-15, 1993)
Keywords :
digital arithmetic; integrated logic circuits; multiplying circuits; number theory; pipeline processing; transforms; Fermat number transform; area-time efficient implementation; diminished-1 multiplier; regular implementation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19941146
