Abstract :
A new statistical circuit design centering and tolerancing methodology based on a synthesis of concepts from network analysis, recent optimization methods, sampling theory, and statistical estimation and hypothesis testing is presented. The method permits incorporation of such realistic manufacturing constraints as tuning, correlation, and end-of-life performance specifications. Changes in design specifications and component cost models can be handled with minimal additional computational requirements. A database containing the results of a few hundred network analyses is first constructed. As the nominal values and tolerances are changed by the optimizer, each new yield and its gradient are evaluated by a new method called Parametric sampling without resorting to additional network analyses. Thus the most costly phase of statistical design,-statistical simulation, may be carried out only once, which leads to considerable computational efficiency. Equivalent or superior designs for intermediate size networks are obtained with less computational effort than previously published methods. For example, a worst-case design for an eleventh-order Chebychev filter gives a filter cost of 44 units, a centered worst-case design reduces the cost to 18 units and statistical design using Parametric sampling further reduces the cost to 5 units (800 analyses, 75 CPU seconds on an IBM 370/158).
