• DocumentCode
    1185855
  • Title

    Neural n-port voltage comparator network

  • Author

    Pedroni, Volnei A.

  • Author_Institution
    Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA
  • Volume
    30
  • Issue
    21
  • fYear
    1994
  • fDate
    10/13/1994 12:00:00 AM
  • Firstpage
    1774
  • Lastpage
    1775
  • Abstract
    Use is made of a neural architecture to realise a low-offset VLSI implementation of an n-port voltage comparator that performs the winner-take-all function. The circuit has a wide resolution (~50 dB), high gain, and a Hopfield-like positive feedback interconnect matrix, making possible the detection of very small perturbations (<10 mV). The circuit is suitable for applications in Hamming and neural networks, vector quantisers, and other analogue parallel signal processing systems. The performance of the network was measured on a 32 input 2.0 μm CMOS circuit
  • Keywords
    CMOS integrated circuits; Hopfield neural nets; VLSI; analogue processing circuits; comparators (circuits); multiport networks; neural chips; parallel architectures; vector quantisation; CMOS circuit; Hamming networks; Hopfield-like positive feedback interconnect matrix; analogue parallel signal processing systems; high gain; low-offset VLSI implementation; n-port voltage comparator network; neural architecture; vector quantisers; wide resolution; winner-take-all function;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19941182
  • Filename
    328523