Study on the board-level drop test of the stacked memory device by FEA

In this study, the drop test simulation for a typical stacked memory device with 8 units integrated vertically on board-level was performed by finite element method. The units were connected with each other through copper lead frames and assembled on the PCB by pins. The computational model of the device was built in ANSYS and the drop test of this board-level assembled device was investigated by numerical method in this study. Using the finite element analysis, the stress in the boardlevel device were predicted under the drop test conditions which is followed the JEDEC standards. In the analysis, appropriate simplification of small structures, e.g. wire bond etc. and the 1/4 model was adopted to overcome the huge computational costs. The results showed the critical locations of the board-level assembled device in the drop test and revealed the most effect parameters. Some suggestions for improving the reliability of POP device were proposed on the basis of the results of computation and analysis.