Title :
A stochastic model for interconnections in custom integrated circuits
Author :
Gamal, Abbas El ; Syed, Zahir A.
fDate :
9/1/1981 12:00:00 AM
Abstract :
A stochastic model for interconnections in integrated circuits composed of unequal size logic blocks separated by routing channels is described. An algorithm, based on the model, is given for estimating channel widths and chip area. The effectiveness of the algorithm is tested through an example. Applications of the model to placement and routing of integrated circuits are discussed.
Keywords :
Computer-aided circuit analysis and design; Layout; Application specific integrated circuits; Circuit testing; Information systems; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit modeling; Laboratories; Logic circuits; Routing; Stochastic processes;
Journal_Title :
Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCS.1981.1085064
