• DocumentCode
    1186381
  • Title

    Simulation and experiments of stress migration for Cu/low-k BEoL

  • Author

    Zhai, Charlie Jun ; Yao, H. Walter ; Marathe, Amit P. ; Besser, Paul R. ; Blish, Richard C.

  • Author_Institution
    Adv. Micro Devices Inc., Sunnyvale, CA, USA
  • Volume
    4
  • Issue
    3
  • fYear
    2004
  • Firstpage
    523
  • Lastpage
    529
  • Abstract
    Stress migration (SM) or stress-induced voiding experiments were conducted for two back-end-of-line (BEoL) technologies: Cu/FTEOS and Cu/low-k. Experiments have shown the mean time to failure (MTF) depends on inter-layer dielectric (ILD) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using finite element analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD properties, ILD stack and metal line width. The concept of an SM risk index is proposed to assess BEoL stress migration reliability from both stress and energy perspectives. Comparison of the SM risk index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress-induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.
  • Keywords
    copper; failure analysis; finite element analysis; integrated circuit reliability; integrated circuit testing; semiconductor process modelling; voids (solid); Cu; Cu/FTEOS; Cu/low-k BEoL; ILD stack; accelerated testing; back-end-of-line technologies; finite element analysis; inter-layer dielectric; line width; materials properties; mean time to failure; metal fine width; process-oriented modeling; reliability testing; risk index; stress migration reliability; stress modeling; stress-driven mechanisms; stress-induced voiding experiments; Finite element methods; Life estimation; Materials testing; Performance evaluation; Power system modeling; Samarium; Semiconductor device modeling; Stress measurement; Temperature; Thermal stresses;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2004.833225
  • Filename
    1369215