A novel ultrathin vertical channel NMOSFET with asymmetric fully overlapped LDD

Author

Liu, Haitao ; Xiong, Zhibin ; Sin, Johnny K O

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

24

Issue

2

fYear

2003

Firstpage

84

Lastpage

86

Abstract

In this letter, a novel ultrathin vertical channel (UTVC) NMOSFET with asymmetric fully overlapped lightly doped drain (LDD) is proposed and demonstrated using solid-phase epitaxy (SPE). A boron-doped polycrystalline Si/sub 0.5/Ge/sub 0.5/ gate was used to tune the threshold voltage, a lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel was used to suppress the electron mobility degradation, and an asymmetric fully overlapped LDD was adopted to reduce the series resistance as compared to the conventional LDD. Devices with 50-nm channel length were achieved by using 15-nm ultrathin channel thickness, and they provided high current drive, steep subthreshold slope, and good V/sub T/ roll-off characteristics.

Keywords

Ge-Si alloys; MOSFET; electron mobility; semiconductor epitaxial layers; semiconductor growth; semiconductor materials; solid phase epitaxial growth; 15 nm; 50 nm; Si/sub 0.5/Ge/sub 0.5/:B; Si/sub 0.5/Ge/sub 0.5/:B gate; asymmetric fully overlapped LDD; electron mobility degradation; high current drive; roll-off characteristics; series resistance; solid-phase epitaxy; subthreshold slope; threshold voltage; ultrathin channel thickness; ultrathin vertical channel NMOSFET; Amorphous silicon; CMOS technology; Degradation; Electron mobility; Epitaxial growth; Etching; Lithography; MOSFET circuits; Substrates; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2002.808153

Filename

1196024