Title :
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM
Author :
Yamashita, Nobuyuki ; Kimura, Tohru ; Fujita, Yoshihiro ; Aimoto, Yoshiharu ; Manabe, Takashi ; Okazaki, Shin´ichiro ; Nakamura, Kazuyuki ; Yamashina, Masakazu
Author_Institution :
Inf. Technol. Res. Lab., NEC Corp., Kanagawa, Japan
fDate :
11/1/1994 12:00:00 AM
Abstract :
An integrated memory array processor (IMAP) ULSI with 64 processing elements and a 2-Mb SRAM has been developed for image processing. The chip attains a 3.84 GIPS peak performance through the use of SIMD parallel processing and a 1.28 GByte/s on-chip processor-memory bandwidth. The IMAP is capable of parallel indirect addressing, which increases applications for parallel algorithms. Large power consumption with the wide memory bandwidth is avoided by reducing the number of active sense amplifiers and adopting dynamic power control. Fabricated with a 0.55-μm BiCMOS double layer metal process technology, the IMAP contains 11 million transistors in a 15.1×15.6 mm2 die area
Keywords :
BiCMOS integrated circuits; SRAM chips; VLSI; amplifiers; image processing; image processing equipment; parallel architectures; 0.55 mum; 1.28 Gbyte/s; BiCMOS double layer metal process technology; GIPS integrated memory array processor; GIPS peak performance; SIMD parallel processing; SRAM; ULSI; active sense amplifiers; die area; dynamic power control; giga instructions per second; image processing; large power consumption; on-chip processor-memory bandwidth; parallel algorithms; parallel indirect addressing; processing elements; transistors; wide memory bandwidth; Bandwidth; BiCMOS integrated circuits; Energy consumption; Image processing; Parallel algorithms; Parallel processing; Power amplifiers; Power control; Random access memory; Ultra large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
