A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

Author

Tamba, Nobuo ; Anzai, Akio ; Akimoto, Kazuhiro ; Ohayashi, Masayuki ; Hiramoto, Toshiro ; Kokubu, Tadanori ; Ohmori, Sohei ; Muraya, Tetsuya ; Kishimoto, Atsuyuki ; Tsuji, Sousuke ; Hayashi, Hideki ; Handa, Nadateru ; Igarashi, Toshio ; Nambu, Hiroaki ; Y

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

Volume

29

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

1344

Lastpage

1352

Abstract

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm

Keywords

BiCMOS integrated circuits; SRAM chips; emitter-coupled logic; integrated logic circuits; 0.5 micron; 1.5 ns; 18 W; 256 kbit; 35 W; 60 ps; BiCMOS SRAM; CMOS memory cells; ECL word driver; emitter-coupled logic; logic gates; logic in memory; low-power active pull down ECL decoder; static RAM; ultra-high-speed access time; BiCMOS integrated circuits; CMOS logic circuits; Decoding; Delay effects; Driver circuits; Energy consumption; Logic functions; Logic gates; Random access memory; Read-write memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.328635

Filename

328635