A 30-ns cycle time 4-Mb mask ROM

Author

Sunaga, Toshio

Author_Institution

Yasu Technol. Applic. Lab., IBM Japan Ltd., Shiga, Japan

Volume

29

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

1353

Lastpage

1358

Abstract

A 4-Mb mask ROM in a 256-Kb×16 organization is described. It is fabricated with a 1.0-μm CMOS process, using single polysilicon, two levels of metal, and 3.0×4.4 μm² X-cells. Unlike conventional ROM´s, it implements a DRAM type RAS/CAS control scheme. A RAS access time of 60 ns is measured. For a fast data access, the chip has a consecutive address read mode in which the system needs to supply only a first address and subsequent addresses are generated in the ROM chip at every CAS clock. A 30-ns cycle time is demonstrated in this mode. 16-b data pins are also used for RAS/CAS multiplexed address inputs. Because of this three way pin multiplexing, the 7.5×10.5 mm² chip needs only 28 pins for its 400-mil SOJ package

Keywords

CMOS integrated circuits; integrated memory circuits; multiplexing; read-only storage; 1 micron; 30 ns; 4 Mbit; 60 ns; CMOS process; DRAM type RAS/CAS control scheme; RAS access time; RAS/CAS multiplexed address inputs; SOJ package; X-cells; consecutive address read mode; mask ROM; single polysilicon two level metal process; three way pin multiplexing; CMOS process; CMOS technology; Clocks; Content addressable storage; Logic arrays; Packaging; Pins; Random access memory; Read only memory; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.328636

Filename

328636