High-speed, low-switching noise CMOS memory data output buffer

Author

Chioffi, Ernestina ; Maloberti, Franco ; Marchesi, Gianmarco ; Torelli, Guido

Author_Institution

SGS-Thomson Microelectron., Milan, Italy

Volume

29

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

1359

Lastpage

1365

Abstract

This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving of the output pull-up and pull-down transistors. Tristate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm² and ensures a better than 15 ns output transition time with a load capacitor of 100 pF

Keywords

CMOS integrated circuits; EPROM; buffer circuits; integrated memory circuits; noise; switching; 15 ns; 16 Mbit; CMOS integrated memories; CMOS memory data output buffer; EPROM device; Si; buffer circuit; high data output pin count; high-speed operation; low-switching noise; output presetting techniques; tristate operation; zero static power consumption; Capacitors; Circuit noise; Delay; EPROM; Energy consumption; Noise generators; Noise reduction; Packaging; Power supplies; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.328637

Filename

328637