DocumentCode
1187350
Title
Testability on TAP
Author
Maunder, Colin M. ; Tulloss, Rodham E.
Author_Institution
BT Lab., Ipswich, UK
Volume
29
Issue
2
fYear
1992
Firstpage
34
Lastpage
37
Abstract
A new approach to testing based on boundary scan is discussed. This technique gives access to individual chip pins by including a little standardized circuitry and a test access port (TAP) on every IC. Boundary scan basics are reviewed, and three principal types of tests that can be performed with the boundary-scan register are described. They are: interconnect tests, using the EXTEST (external test) instruction; chip tests, using the INTEST instruction; and sampling, using the SAMPLE instruction.<>
Keywords
automatic testing; integrated circuit testing; EXTEST instruction; IC; INTEST instruction; SAMPLE instruction; boundary scan; chip tests; interconnect tests; sampling; test access port; Automatic testing; Circuit testing; Costs; Integrated circuit testing; Logic testing; Manufacturing automation; Pins; Standards development; System testing; Test equipment;
fLanguage
English
Journal_Title
Spectrum, IEEE
Publisher
ieee
ISSN
0018-9235
Type
jour
DOI
10.1109/6.119610
Filename
119610
Link To Document