Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Author

Xiongbo Zhao ; Penglong Jiang ; Liangliang Liu

Author_Institution

Nat. Key Lab. of Sci. & Technol. on Aerosp. Intell. Control, Beijing, China

fYear

2014

fDate

12-15 Aug. 2014

Firstpage

1108

Lastpage

1111

Abstract

A SiP(System in Package) consists of multiple chips stacked and connected within a package. And SiP testing is a significant and growing problem owing to the limited accessibility and its particular test flow. It requires individual chip-level, interconnections test, post-packaging test and final system testing. This paper presents an overview of SiP test flow and the problem encountered by SiP test, and suggests its solution - the IEEE 1500 Standard for Embedded Core Test (SECT). IEEE 1500 provides test access structure and mechanisms to implement the parallel scheduling test for hierarchical SiP.

Keywords

IEEE standards; scheduling; system-in-package; IEEE 1500 SECT; IEEE 1500 standard for embedded core test; SiP test flow; chip-level; final system testing; hierarchical SiP test; interconnection test; parallel scheduling strategy; post-packaging test; system-in-package; test access structure; IEEE standards; Integrated circuit interconnections; Packaging; System-on-chip; Test equipment; IEEE 1500 Standard; SiP test; parallel test;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology (ICEPT), 2014 15th International Conference on

Conference_Location

Chengdu

Type

conf

DOI

10.1109/ICEPT.2014.6922838

Filename

6922838