A parallel algorithm for time-slot assignment problems in TDM hierarchical switching systems

Author

Funabiki, Nobuo ; Takefuji, Yoshiyasu

Author_Institution

Div. of Syst. Eng., Sumitomo Metal Ind. Ltd., Amagasaki, Japan

Volume

42

Issue

10

fYear

1994

fDate

10/1/1994 12:00:00 AM

Firstpage

2890

Lastpage

2898

Abstract

The paper presents a parallel algorithm for time-slot assignment problems in TDM hierarchical switching systems, based on the neural network model. The TDM systems are operated in repetitive frames composed of several time-slots. A time-slot represents a switching configuration where one packet is transmitted through an I/O line. The goal of the algorithm is to find conflict-free time-slot assignments for given switching demands. The algorithm runs on a maximum of n²×m processors for m-time-slot problems in n×n TDM systems. In small problems up to a 24×24 TDM system, the algorithm can find the optimum solution in a nearly constant time, when it is performed on n²×m processors

Keywords

hierarchical systems; minimisation of switching nets; neural nets; packet switching; parallel algorithms; telecommunication traffic; I/O line; TDM hierarchical switching systems; conflict-free time-slot assignments; neural network model; packet; parallel algorithm; repetitive frames; switching configuration; switching demands; time-slot assignment problems; Hierarchical systems; Intelligent networks; Neural networks; Packet switching; Parallel algorithms; Satellites; Switches; Switching systems; Telecommunication traffic; Time division multiplexing;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.328959

Filename

328959