• DocumentCode
    1188260
  • Title

    Reticle Design for Minimizing Multiproject Wafer Production Cost

  • Author

    Lin, Rung-Bin ; Wu, Meng-Chiou ; Tsai, Shih-Cheng

  • Author_Institution
    Yuan Ze Univ., Chung-Li
  • Volume
    4
  • Issue
    4
  • fYear
    2007
  • Firstpage
    589
  • Lastpage
    595
  • Abstract
    Multiproject wafer (MPW) production cost is sensitive to how the chips are arranged in a reticle. In this paper, we propose a methodology for exploring the reticle floorplan design space to minimize MPW production cost. Experimental results show that our methodology often achieves double-digit cost savings. A study using MPW for volume production shows that the volume cutoff points range from a few thousand dice to tens of thousands of dice. Note to Practitioners-This paper proposes a methodology for minimizing MPW production cost via better chip placement in a reticle (called reticle floorplanning). Our methodology consists of an effective reticle floorplanning method, two simulated wafer dicing methods, two cost estimation models, and a procedure for calculating the cost assumed by each project. A design service company or a foundry can use our methodology to reduce MPW production cost and, thus, provides a more affordable and expedient service to its customers. The reticle floorplanning method and simulated wafer dicing methods employed here are the state-of-the-art. A practitioner should adapt these methods to other MPW problems such as dealing with multitechnology process, placing multiple instances of the same design in a reticle, etc. The cost models should also be revised accordingly. The cost data given in this paper should be used only for reference as mask tooling and wafer fabrication costs constantly change. The cost model proposed for calculating the production cost assumed by each project can serve as a basis for developing a fairer pricing model. The study of using MPW for low to medium-volume production is also very useful. It may help a customer deliver its product earlier to market using a low-cost fabrication program. The problem addressed in this paper becomes much simpler if the side-to-side wafer dicing constraint is removed.
  • Keywords
    cost reduction; design engineering; integrated circuit design; integrated circuit manufacture; reticles; cost savings; multiproject wafer production cost minimization; reticle floorplan design space; simulated wafer dicing methods; volume cutoff points; Automation; Costs; Fabrication; Foundries; Optimization methods; Pricing; Production; Prototypes; Semiconductor device modeling; Semiconductor devices; Design automation; masks; optimization methods; semiconductor device fabrication;
  • fLanguage
    English
  • Journal_Title
    Automation Science and Engineering, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1545-5955
  • Type

    jour

  • DOI
    10.1109/TASE.2007.904239
  • Filename
    4312831