DocumentCode :
1188496
Title :
Slicing floorplan with clustering constraint
Author :
Yuen, W.S. ; Young, Evangeline F Y
Author_Institution :
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China
Volume :
22
Issue :
5
fYear :
2003
fDate :
5/1/2003 12:00:00 AM
Firstpage :
652
Lastpage :
658
Abstract :
In floorplan design, it is useful to allow users to specify some placement constraints in the final packing. Clustering constraint is a popular type of placement constraint in which a given set of modules are restricted to be placed adjacent to one another. The wiring cost can be reduced by placing modules with a lot of interconnections closely together. Designers may also need this type of constraint to restrict the positions of some modules according to their functionalities. In this paper, a method addressing clustering constraint in slicing floorplan is presented. We devised a linear time algorithm to locate neighboring modules in a normalized Polish expression and to rearrange them to satisfy the given constraints. Experiments were performed on some benchmarks and the results are very promising.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; modules; CAD; VLSI; benchmarks; clustering constraint; final packing; linear time algorithm; module functionalities; modules; neighboring modules; normalized Polish expression; placement constraints; slicing floorplan; wiring cost; Algorithm design and analysis; Clustering algorithms; Combinational circuits; Delay effects; Induction generators; Minimization methods; Polynomials; Sorting;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.810738
Filename :
1196209
Link To Document :
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