A transition-encoded dynamic bus technique for high-performance interconnects

Author

Anders, Mark ; Rai, Nivruti ; Krishnamurthy, Ram K. ; Borkar, Shekhar

Author_Institution

Circuits Res., Intel Corp., Hillsboro, OR, USA

Volume

38

Issue

5

fYear

2003

fDate

5/1/2003 12:00:00 AM

Firstpage

709

Lastpage

714

Abstract

This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique.

Keywords

delays; integrated circuit design; integrated circuit interconnections; low-power electronics; microprocessor chips; 180 nm; 32 bit; drop-in replacement; energy savings; global buses; high-performance interconnects; microprocessor data path blocks; on-chip interconnect delay reduction; peak-current reduction; robustness; short-length buses; switching energy behavior; transition-encoded dynamic bus technique; Capacitance; Coupling circuits; Delay; Driver circuits; Encoding; Integrated circuit interconnections; Microprocessors; Robustness; Switches; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.810061

Filename

1196215