Threshold-voltage balance for minimum supply operation [LV CMOS chips]

Author

Ono, Goichi ; Miyazaki, Masayuki

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

38

Issue

5

fYear

2003

fDate

5/1/2003 12:00:00 AM

Firstpage

830

Lastpage

833

Abstract

The difference between the threshold voltages V_t of pMOS and nMOS transistors is a critical issue in the low-voltage operation of CMOS circuits. The pMOS/nMOS V_t balancing profit is analyzed in terms of subthreshold leakage current and the performance of CMOS LSIs and the minimum supply voltage of logic circuits. Matching the pMOS/nMOS V_t improves LSI performance and reduces the lowest supply voltage by 0.15 V. We propose a new concept of body bias management that uses forward biasing, fluctuation compensating, and V_t matching technologies to resolve the issue.

Keywords

CMOS integrated circuits; VLSI; leakage currents; low-power electronics; system-on-chip; CMOS chip performance; SoC; body bias management; fluctuation compensation; forward biasing; low-power system LSIs; low-voltage operation; minimum supply operation; nMOS transistors; pMOS transistors; subthreshold leakage current; threshold voltage matching; threshold-voltage balance; CMOS logic circuits; Fluctuations; Large scale integration; Logic circuits; MOS devices; MOSFETs; Performance analysis; Subthreshold current; Technology management; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.810043

Filename

1196230