DocumentCode
1188718
Title
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique
Author
Ye, Yibin ; Khellah, Muhammad ; Somasekhar, Dinesh ; Farhang, Ali ; De, Vivek
Author_Institution
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
Volume
38
Issue
5
fYear
2003
fDate
5/1/2003 12:00:00 AM
Firstpage
839
Lastpage
842
Abstract
This work describes an aggressive SRAM cell configuration using dual-VT and minimum channel length to achieve high performance. A bitline leakage reduction technique is incorporated into an L1 cache design using the new cell in a 100-nm dual-VT technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6-GHz operation at with 15% higher energy.
Keywords
CMOS memory circuits; SRAM chips; cache storage; circuit stability; leakage currents; very high speed integrated circuits; 100 nm; 16 kB; 6 GHz; L1 cache design; aggressive SRAM cell configuration; bitline leakage reduction technique; cell read current; cell stability; dual threshold voltage; dual-VT technology; minimum channel length; noise margin; wordline underdrive; Clocks; Delay; Frequency; Laboratories; Leakage current; Microprocessors; Noise reduction; Random access memory; Stability; Threshold voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2003.810057
Filename
1196232
Link To Document