DocumentCode
1188766
Title
Annealing behavior of linear bipolar devices with enhanced low-dose-rate sensitivity
Author
Shaneyfelt, Marty R. ; Schwank, James R. ; Fleetwood, Dan M. ; Pease, Ronald L. ; Felix, James A. ; Dodd, Paul E. ; Maher, Michael C.
Author_Institution
Sandia Nat. Labs., Albuquerque, NM, USA
Volume
51
Issue
6
fYear
2004
Firstpage
3172
Lastpage
3177
Abstract
The post-irradiation annealing behavior of total dose degradation in LM139 comparators fabricated in National Semiconductor Corporation´s (NSC) enhanced low-dose-rate sensitive (ELDRS) linear bipolar technology is examined. Data show that a large fraction of the radiation-induced increase in input bias current recovers after a 100°C anneal. The recovery in input bias current is linked to a significant amount of interface-trap annealing at 100°C. This is qualitatively consistent with previous data on interface-trap annealing and recent models for interface-trap annealing associated with hydrogen motion at the silicon/silcon dioxide interface. The annealing results have implications for hardness assurance testing. If the radiation induced charge that is responsible for ELDRS (whether it be interface or border traps) can anneal at 100°C, these data suggest that elevated temperature irradiations sometimes used to bound the ELDRS response of ICs may also cause some annealing of radiation-induced charge. These data help explain why high-dose-rate irradiations at elevated temperatures in some cases underestimate low-dose-rate degradation. In addition, these data confirm that high-dose-rate irradiations followed by elevated temperature anneals do not mimic the mechanisms that cause enhanced degradation at low dose rates in devices with ELDRS.
Keywords
annealing; bipolar integrated circuits; dosimetry; integrated circuit reliability; integrated circuit testing; interface states; passivation; radiation hardening (electronics); semiconductor device measurement; thermal stresses; 100 C; LM139 comparators; Si-SiO2; annealing behavior; bipolar linear integrated circuits; defect annealing; elevated temperature irradiations; enhanced low-dose-rate sensitivity; hardness assurance testing; high-dose-rate irradiations; hydrogen motion; input bias current; integrated circuit reliability; integrated circuit testing; interface-trap annealing; linear bipolar devices; low-dose-rate degradation; passivation layers; postirradiation annealing behavior; preirradiation elevated temperature stress; radiation effects; radiation hardening (electronics); radiation induced charge; radiation response; silicon-silicon dioxide interface; thermal cycling; thermal stress effects; total dose degradation; Annealing; CMOS technology; Circuit testing; Degradation; Electronic equipment testing; Integrated circuit testing; Laboratories; Substrates; Temperature sensors; Thermal stresses;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2004.839200
Filename
1369466
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