Title :
On determining symmetries in inputs of logic circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
11/1/1994 12:00:00 AM
Abstract :
We propose a method for computing maximal sets of symmetric inputs in logic circuits, using a test generation procedure for single stuck-at faults. The method is enhanced by a heuristic that can be used to identify nonsymmetric inputs and thus reduce the number of inputs for which test generation has to be carried out. We show the relevance of the problem to input matching for design diagnosis and for technology mapping. Experimental results demonstrate the effectiveness of the proposed procedures
Keywords :
logic design; logic testing; set theory; design diagnosis; input matching; logic circuits; maximal sets; single stuck-at faults; symmetric inputs; technology mapping; test generation procedure; Circuit faults; Circuit testing; Cities and towns; Impedance matching; Libraries; Logic circuits; Logic design; Logic functions; Logic testing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
