• DocumentCode
    1189061
  • Title

    Single event transients characterization in SOI CMOS comparators

  • Author

    Zhao, Bing ; Leuciuc, Adrian

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY, USA
  • Volume
    51
  • Issue
    6
  • fYear
    2004
  • Firstpage
    3360
  • Lastpage
    3364
  • Abstract
    A theoretical analysis of single event induced transients in SOI CMOS comparators is presented, confirmed by transistor-level simulations. The proposed approach can predict the probability of single event upset (SEU) at the output of the comparator. A design methodology to achieve an imposed radiation hardness is proposed.
  • Keywords
    CMOS analogue integrated circuits; CMOS digital integrated circuits; comparators (circuits); integrated circuit design; radiation hardening (electronics); silicon-on-insulator; transients; SEU; SOI CMOS comparators; probability; radiation hardness; single event transients characterization; single event upset; transistor-level simulations; Analog circuits; CMOS technology; Capacitance; Circuit simulation; Circuit synthesis; Digital circuits; Latches; Single event upset; Space technology; Voltage;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2004.839508
  • Filename
    1369495
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1189061