SET tolerant CMOS comparator

A novel way to mitigate single event transients (SETs) in a comparator by using auto-zeroing techniques is presented. Two comparators, a folded cascode comparator and a novel auto-zeroed comparator, are simulated using a current pulse model for a single event strike. These simulations show that the novel auto-zeroed comparator transients are never longer in duration than a single auto-zero clock period. This compares favorably to a folded cascode comparator sample circuit, whose maximum transient duration is strongly dependent on the differential input voltage and can be four times as long. The use of the presented auto zero comparator can practically eliminate the comparator contribution to single event errors in many mixed signal circuits, such as analog-to-digital converters (ADCs).