• DocumentCode
    1189718
  • Title

    An Attempt to Design an Improved Multiplication System

  • Author

    Harman, M.G.

  • Issue
    11
  • fYear
    1968
  • Firstpage
    1090
  • Lastpage
    1090
  • Abstract
    Abstract—A speeded-up multiplication technique is considered wherein the two numbers to be multiplied are first examined and the one with the fewer 1´s is selected as the multiplier. It is found that the speeding-up diminishes towards 0 as the word length increases.
  • Keywords
    Index Terms—Algorithm, binary multiplication, series-parallel multiplication.; Circuits; Equations; Index Terms—Algorithm, binary multiplication, series-parallel multiplication.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1968.226864
  • Filename
    1687268
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1189718