DocumentCode
1189723
Title
Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"
Author
Davidson, Edward S. ; Metze, Gernot
Author_Institution
IEEE
Issue
11
fYear
1968
Firstpage
1091
Lastpage
1092
Abstract
Abstract—The principal synthesis example of Schneider and Dietmeyer´s paper [1] is examined by applying a new synthesis algorithm. The minimum NOR gate realization thus obtained is used to illustrate the nonoptimality of their approach and to question their definition of delay. Arguments are advanced for synthesis with simple modules.
Keywords
Index Terms—Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.; Algorithm design and analysis; Circuit synthesis; Combinational circuits; Costs; Delay; Design automation; Libraries; Logic design; Packaging; Upper bound; Index Terms—Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1968.226866
Filename
1687269
Link To Document