Sense amplifier based RADHARD flip flop design

Author

Wang, Weizhong ; Gong, Haiyan

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Univ. of Wisconsin-Milwaukee, Milwaukee, WI, USA

Volume

51

Issue

6

fYear

2004

Firstpage

3811

Lastpage

3815

Abstract

In this paper, a sense amplifier based radiation hardening (RADHARD) flip flop design is presented. The sense amplifier based master stage reduces the loading to the clock network. The proposed improvement on the slave stage shortens the data to Q delay. The simulation results indicate that the proposed design has a shorter data to Q delay than the flip flop design used in Alpha 21264 microprocessors. The proposed design can be fabricated in the mainstream commercial digital complementary metal oxide semiconductor process.

Keywords

CMOS logic circuits; clocks; delay circuits; digital circuits; flip-flops; microprocessor chips; radiation hardening (electronics); sequential circuits; Alpha 21264 microprocessors; Q delay; clock network; digital circuits; mainstream commercial digital complementary metal oxide semiconductor process; registers; sense amplifier based master stage; sense amplifier based radiation hardening flip flop design; sequential logic circuit fault tolerance; shorter data; single-event effects; single-event transients; slave stage; CMOS technology; Clocks; Delay; Digital systems; Error analysis; Frequency; Logic devices; Microprocessors; Radiation hardening; Sequential circuits;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2004.839149

Filename

1369563